1. Field of the Invention
The present invention relates generally to the packaging of electronic components. More particularly, the present invention relates to a wafer level package and method of fabricating the same.
2. Description of the Related Art
One form of an electronic component package included an electronic component such as an integrated circuit chip mounted to a substrate. For example, in a wirebond configuration, the rear surface of the integrated circuit chip was mounted to the substrate, e.g., with an adhesive. Bond wires were used to form the electrical interconnections between the bond pads on the front surface of the integrated circuit chip and the electrically conductive traces on the substrate.
As the art moved to smaller and lighter weight electronic devices, it became increasingly important that the size of the electronic component package used within these electronic devices was small. However, in the wirebond configuration described above, the traces of the substrate were fanned out around the integrated circuit chip, which placed a fundamental restriction on the minimum electronic component package size. Further, a large impedance was associated with the bond wires.
To allow a further reduction in the electronic component package size as well as to reduce impedance of the interconnections, a flip chip configuration was used instead of a wirebond configuration. In a flip chip configuration, the bond pads on the front surface of the integrated circuit chip were directly connected to the traces on the substrate with flip chip bumps, e.g., solder. This avoided the need to fan out the traces around the integrated circuit chip resulting in a minimum package size. Further, the use of flip chip bumps between the bond pads and the traces on the substrate minimized impedance.
However, the flip chip bumps between the bond pads of the integrated circuit chip and the traces on the substrate were subject to significant stress, e.g., due to differential thermal expansion between the integrated circuit chip and the substrate. Thus, failure of the flip chip bumps often occurred which decreased yield and thus increased the cost of the electronic component package.
To minimize the failure of the flip chip bumps, an underfill material was often applied between the integrated circuit chip and the substrate and around the flip chip bumps. However, the application of the underfill material required an additional manufacturing step, which increased the cost of the electronic component package.